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Generation Network Processors
processors are ushering in a new era of performance and flexibility
in networking. Here is an overview of the functions of network
processors and the different vendors in the arena
processors offer a solution that can help maximize bandwidth
utilization and traffic flow
defined, a network processor is a programmable device, typically
a chip, that has been designed and highly optimized to perform
processors are suitable for the tasks that handle heavy streams
of data as well. In the near future network processors will
be able to handle all the 7 layer functions at wire speeds
fundamental shift is occurring in the network hardware manufacturing
marketplace as demands for very high-speed, service enabled
eclipse those for more traditional
layer 2/3 routing and switching offerings. The combination
of hardware acceleration, direct support
for features that run the gamut from QoS to encryption to
Service Level Agreement (SLA) monitoring
and reporting, coupled with demands for longer product lifecycles
with reduced time to market,
have given birth to the programmable network processor industry.
vendors are in desperate
need for an "adjunct" processing
solution that addresses both current and future challenges
in network evolution. Successfully meeting these challenges
through standard products is key to
maintaining a competitive position in the market.
In today's networked world, bandwidth
is a critical resource. Increasing network traffic, driven
by the Internet and other emerging applications, is straining
the capacity of communication lines and semiconductor
technologies. To keep pace, organizations are looking for
better technologies and methodologies to support and manage
traffic growth and the convergence of voice and data. Network
processors offer a solution that can help maximize bandwidth
utilization and traffic flow. Then, the question: what is
a network processor?
Network processors are many things to different people.
Loosely defined, a network processor is a programmable device
a chip) that has been designed and highly optimized to perform
networking functions. Unfortunately the term has also been
applied to an assortment of
products (including ASICs and
to a lesser degree to FPGAs) designed to deliver some form
classification or rudimentary QOS
in a network environment.
A network processor is composed of
two distinct sets of hardware functional
units combined with highly
optimized software that supports
both system-level and network-specific
NPUs also need several high bandwidth interfaces, as their
main function is to move data from one place to another.
These chips typically have about five Gbps of input bandwidth,
five Gbps of output bandwidth, and 10 Gbps of memory (DRAM)
bandwidth. The total bandwidth is three times that of a Pentium
Evolution of Network Processors
the late 1990s, most network routers were based on architecture
similar to a personal computer. A CPU performed tasks such
as forwarding table lookups, access control filtering and
processing of routing updates. The central processor received
instructions from the router operating system that ran in
the RAM, along with basic instructions stored in the ROM.
The advantage of this architecture was that all instructions
were stored in software; thereby enabling the addition of
new features by simply
upgrading the system software. However, the drawback to software-based
solutions was their limited ability to scale to support the
demands of higher bandwidth and additional features.
Application Specific ICs (ASICs)
came the emergence of the ASIC paradigm. Many Layer 2 switches
employed custom Application Specific Integrated Circuits (ASICs),
Digital Signal Processors (DSP) or Reduced Instruction Set
Computing (RISC)-based processors. Hardware
manufacturers found that instead of using software based processing,
they could achieve tremendous
performance improvements by creating specialized chips that
with embedded instructions. These chips could therefore perform
forwarding decisions in the hardware itself. ASIC based switching
has allowed for a new generation of very high-speed routers
In the days of software-based routers and bridges there was
no need for a specialized network processor. However, in order
acceptable performance to handle higher speed technologies
such as Fast and Gigabit Ethernet, specialized network processors
are required. Network processors fulfill the need that CPUs
and ASICs failed to meet. These processors are highly specialized
integrated circuits that handle the wire-speed data path and
perform protocol classification and analysis.
functions performed by network processors include:
Segmentation Assembly and Reassembly (SAR): Frames are
processed and then reassembled for forwarding.
Protocol Recognition and Classification: Frames are identified
based on protocol type, port-number, destination URL or
other application/protocol specific information.
Queuing and Access Control: The identified frames are
placed in appropriate queues for further processing. They
are also checked against security access policy rules
to see if they should be forwarded or discarded.
Traffic Shaping and Engineering: Traffic is 'shaped' to
ensure that it meets the required delay (or delay variation
Quality of Service (QOS)
In most routers, for example, the host CPU handles the network-management
functions and the routing of data in the lookup address table
in the system itself. But packet processing is typically done
not hardware, thereby causing
one of the biggest problems latency. Network processors are
one of the methods to solve the latency or delay problems.
Some of the basic requirements of a Network Processor are:
Programmability: The network processor must be easily
programmable in order to support customization
of feature sets and the rapid integration of new and existing
technologies. It should enable the design of products
that can dynamically handle different kinds of traffic
Performance: Network processors should be able to rapidly
scale their performance capabilities to support ever-increasing
They should be able to track and support thousands of
Management: Performing management tasks such as identification,
classification and accounting of traffic.
Design Tradeoffs in Delivering Packet Processing Power Networking
and data communications systems have some of the highest
performance requirements in the spectrum of embedded applications.
To process packets as efficiently as possible, a networking
system incorporates multiple processors,
specialized hardware, and highly sophisticated software.
The tradeoffs made between implementing functions in hardware
versus software have a huge impact on overall system performance.
The challenge for new networking equipment
is to create the best of both worlds by performing sophisticated
packet processing at wire speed. Functions implemented in
hardware limit flexibility, while functions implemented in
software limit system performance. Hardware implementation
of features like QoS and security are risky since, standards
in these areas are still evolving. The challenge ahead for
the network processor vendors in designing a better performing,
cost effective, time to market NP has quite a few tradeoffs.
The first tradeoff between hardware and software involves
packet classification. This can be done with software by comparing
a number of different fields, but because Layer 2 Ethernet
and Layer 3 IP classification are well defined, these functions
are suited to hardware acceleration. Because of high packet
volume and the need to classify and process packets at wire
speed, hardware acceleration has become the industry standard
method. In one implementation, hardware acceleration is provided
for Layer 2/3 classification while flexible software provides
for processing at higher layers.
ever-increasing volume of packets to be processed, spurs demand
for additional processing power. The optimal way to increase
processing power is not to build a single processor that is
10 or 20 times faster, but rather to employ multiple processors
and allocate packets among them. One difficulty with this
approach is that related packets must go out in the same order
in which they were received. If two related packets are processed
on separate processors, it is possible that the first packet
could take longer than the second, and the packets could become
unordered. So proper scaling is needed in implementing distributed
analysis of real packet processing applications reveals that
certain software functions can be accelerated through the
of a set of special-purpose processor instructions for protocol
processing and data handling.
Given the results of this particular investigative effort,
one vendor chose to implement a special set of processor instructions
Packet Data Management
packet processing, a relatively small amount of data, the
header, needs to be evaluated. The rest of the data the payload
must simply be moved efficiently through the system from input
to output. Software is inefficient for moving data. It's much
more efficient for hardware to separate
the header from the payload
and deliver the header directly to the processor's memory.
The payload is managed using specialized
hardware to move it directly in and out of main memory, eliminating
the need for CPU intervention.
Data Plane versus Control Plane
tradeoff involves data
plane (fast path) versus control
plane (slow path) operations. Fast-path operations, such as
classification, lookups, or priority checking, must be done
on every packet at wire speed.
critical operation in packet processing
is table lookups. Acceleration is becoming more and more critical
as systems need to provide
sophisticated QoS functions that require additional lookups
farther up the OSI stack. The memory access required for table
lookups (addresses, routes, or flows) should be optimized
in hardware with coprocessor support that accelerates this
Memory Capability and Expansion
bandwidth heavily influences
the number of packets per second that can be processed by
the network. Different memory architectures can provide very
different utilization levels. As route tables grow and sparse
tables are needed to assist in optimizing lookups, the amount
of memory required also increases.
packet egress functions is the final area of tradeoff. The
actual QoS process of selecting packets, discarding packets,
and rate limiting flows must be done as the packet is leaving
the system after processing. A combination
of specialized hardware functions and software configuration
must be implemented at the output point to manage the QoS
Will Network Processors Make An Impact?
processors that handle a range of chores in routers, switches
and telecommunications gear will climb from the "obscurity"
of $128 million in sales last year to about $2.9 billion in
sales by 2004, according to a new market report from Cahners
In-Stat Group. Cahners In-Stat says network processor revenues
would increase at a compound annual growth rate of nearly
63 percent between 1999 and 2004.
strength of network processors is that they're programmable
off-the-shelf parts specifically created for networking applications.
Over time, they will almost certainly displace
general-purpose CPUs and ASICs. Network processors have a
performance advantage over CPU architectures designed years
ago for other tasks, and those have numerous advantages over
Application Specific Integrated Circuits (ASICs).
Network processors are suitable for the tasks that handle
heavy streams of data as well. In the near future network
processors can handle
all the 7 layer functions at wire speeds.
Just as nobody envisioned all of the applications for PC processors
when they first appeared in the 1970s, it's shortsighted to
assume that all the applications of network processors are
known to us today. It is most certain that the demands on
network processors will definitely scale over the next several
years due to demand for more bandwidth and demand by carriers
to provide new services.
Network processors are leading the networking revolution
in the same way PC processors lead the computer revolution.
Hardwired performance, programmability of deep packet
processing, differentiated solutions are some of the advantages
that network processors offer.
Software reuse and portability is another consequence
of the use of network processors. Traditional ASICs are
still not gone but surely they are ill. Network processors
have broken the trade-off performance vs. flexibility
previously imposed by ASICs and general-purpose processors.
Open software interfaces encourage third party development;
therefore the support to standards for network processors
interoperability and functionality will grow in the coming
The Internet network, as we know today, will never be
the same due to the shift of intelligence from the end
hosts to the edge routers and eventually to the core routers
and the whole network. The speed of this shift depends
on the improvements in the network processor's speed and
Network processors are creating a huge array of opportunities
that could be exploited by future startups or spin-offs.
Examples of unexplored opportunities are application aware
switching, high-speed cryptography, VPNs at wire speed,
high speed firewalling, etc.
The final winner in the network processor industry will
be that company which will be able to quickly deliver
price-competitive products to meet market requirements,
supports all of the applications and interfaces of the
value chain and focuses on superior customer service,
supply chain management and marketing programs.
network processor market is still in its early stages. The
explosive growth of the Internet and e-business requires faster
deployment of high-bandwidth equipment and greater flexibility
to support new Internet technologies. The capabilities provided
by the network processor helps in quickly incorporating new
technologies. Here are a few network processors available
in the market.
In 1989, Motorola rolled out what could be considered
the world's first network processor, a 68,000-based CISC
chip that provided a modest 6 MIPS of performance.
IBM launched a new family of network processor chips called
NP4GSX. This family of programmable communications chips
for data networking products such as routers, hubs, and
switches are designed to be enhanced using software rather
than costly hardware upgrades.
Intel Corporation's IXP1200 Network Processor product
line is capable of processing three million packets of
data per second.
The C-5 Digital Communication Processor (DCP), the first
member of the C-Port DCP family of communication processors
is specially designed for networking applications.
Agere's (www.agere.com) functional processor combines
the flexibility of RISC with the performance of ASIC.
The architecture is capable of supporting bandwidth speeds
of OC-192 and beyond while still maintaining the flexibility
and programmability of a traditional RISC processor. Currently
acquired by Lucent Technologies.
XPIF 300 is a gigabit rate packet processor from MMC Networks
(www.mmcnet.com). It has multitasking architecture and
provides wire speed packet processing at gigabit rates.
It supports wire speed Layer 3+ packet processing, with
a throughput of 1.5 million packets per second.
EZchip (www.ezchip.com) Technologies has introduced an
innovative technology called TOP core, for application-level
switching while maintaining Gigabit and Terabit speeds
as a foundation for network-specific processors.
NPUs get networking products to market faster by eliminating
long ASIC design cycles. An ASIC typically takes 18-24 months
to design and debug. The vendor must write software for the
NPU. For the first NPU product, writing the necessary software
may take as long as 12 months, but follow-on products could
take lesser time.
Furthermore, the NPU software can be easily updated to
include new features, new standards, or new protocols,
by its programmability. Bugs and other errors can be repaired
in the field simply by downloading new NPU software.
NPUs can offer better scalability than ASICs. Because
an NPU includes several on-chip processors, its performance
can be increased or decreased simply by adding or removing
Hari, Sr. Software Engineer, Huawei Technologies India Pvt.
Ltd., can be reached at firstname.lastname@example.org